Semiconductor devices, particularly those semiconductor devices formed of a plurality of discrete or electrically interconnected micron-scale, solid state semiconductor elements such as transistors, diodes and the like may be rapidly fabricated by high volume processing techniques which combine steps of photolithography and chemical etching to create preselected patterns of semiconductor alloy material, electrically insulating material and electrically conducting material. These materials cooperate to define various arrays of said discrete or electrically interconnected solid state semiconductor elements.
Typically, such micron-scale semiconductor elements are fabricated by successively depositing and pattern-wise etching various component layers of the materials which combine to form the device. The method of patterning usually includes a photolithographic step by which a protective pattern of photoresist material is provided in intimate contact with a layer of metallic, semiconductor or insulator material so as to define the desired pattern thereof. Subsequently, the entire body of photoresist patterned material is exposed to an etching reagent which may be an aqueous, gaseous or ionic etchant, said etchant functioning to remove the material which is not protected by the photoresist. In subsequent steps, the protective photoresist pattern may be stripped away and further patterned layers may be provided atop the previously patterned layers so as to form the desired device configuration.
In order to provide the photoresist material in the appropriately patterned configuration, photomasking steps are typically employed. In some instances, a mask akin to a photographic negative, having the precise pattern to be formed is typically disposed in superposed and contacting relationship to a photoresist coated layer. The photoresist is then exposed through the mask to radiation which alters its physical properties such that upon subsequent development and processing, the photoresist material is removed in a pattern-wise manner.
In a variant of this process, a mask is placed in a projector and the masking pattern is projected onto the photoresist layer by a noncontact technique, after which the same development steps as outlined for the negative photoresist are utilized. It should be readily appreciated that precise placement of the photolithographic pattern is essential in order to achieve micron-scale device geometry which provides 100% yields. Furthermore, when several photolithographic steps must be sequentially carried out on superposed layers, the relative positioning of the various patterns, generally referred to as registration, becomes increasingly difficult and susceptible to incremental errors.
As alluded to hereinabove, problems of pattern alignment and registration are particularly critical for the production of micron-scale solid state semiconductor elements such as those encountered in integrated circuits or in high density device arrays. Alignment and registration becomes correspondingly difficult and particularly critical as the size of the semiconductor device and the number of small area circuit elements increases. Further, requirements of alignment and registration impose severe cost restrictions in terms of both time and money which must be considered in deciding whether the fabrication of such semiconductor devices is economically feasible. Mask aligning equipment capable of providing the requisite accuracy is quite expensive as well as being difficult and time consuming to operate.
Flat panel displays represent one type of semiconductor product which operates at low voltages with low power consumption. Such displays accordingly enjoy a rapidly expanding market forecast for uses such as computer display terminals, television sets, instrument panels and any other such application in which graphic information must be displayed. High resolution is obviously an essential feature which must be incorporated in such displays in order for the forecasted market potential to become a reality. One way of achieving the requisite degree of resolution is by utilizing active matrix, liquid crystal display technology. For purposes of the subject application, the term, active matrix will mean an array of small area picture elements, each of which incorporates a solid state semiconductor switch therein. By utilizing such active matrix technology, the amount of charge at any given picture element or pixel can be precisely controlled with concommitant control of the transmittance or reflectance of light at that pixel so as to produce high resolution large area displays with gray scale and color capability. To be of practical use, flat panel display devices must be fabricated with a relatively large surface area, typically 400 cm.sup.2 or more. Since, in active matrix technology, each of the pixels of a large area device, will include a switching element, it should be appreciated that a number of photolithographic masking and etching steps must be utilized in a high yield manner in order to fabricate and electrically interconnect those switching elements.
Another technology utilizing large area arrays of solid state circuit elements is that of photosensors. While single discrete diode or transistor elements may be utilized to sense the presence, absence or level of illumination incident thereupon, such devices are even more useful when arranged in linear or two dimensional arrays. By utilizing an array of such solid state circuit elements, large area image scanners may be fabricated which are capable of sensing patterns of illumination. Obviously, such scanner devices have great economic potential for use in facsimile devices, copying machines, page readers, computer input devices as well as other data reading applications. Image scanners are basically a large array of photosensing elements electrically interconnected by associated circuitry for the reading, processing and generating of digital signals.
Large area arrays of solid state semiconductor devices such as those used in active matrix liquid crystal displays and in photosensors require extremely high accuracy of alignment in the photolithographic mask steps by which the micron-scale solid state circuit elements are fabricated on a substrate of up to 400 square centimeters in surface area. Minute errors in alignment multiplied over the large surface area can result in the fabrication of an inoperative overall device. One particular solid state circuit element which is commmonly utilized in large area display and sensor arrays is a thin film diode which includes two metallic electrodes having operatively disposed therebetween a sandwich comprised of at least two superposed layers of thin film semiconductor alloy material. When disposed in array form, such solid state circuit elements typically have at least a top surface thereof covered by a thin insulating layer formed of silicon oxide, silicon nitride or other such dielectric material. The insulating layer includes a centrally located contact hole therein, through which electrical connection is established to the electrode of the micron-scale diode element. In such arrays, the most critical alignment step is, in general, the fabrication of the contact holes through the top insulating layer. For example, when the surface area of each of the diode elements is on the order of 20.times.20 microns and the contact hole is on the order of 10.times.10 microns and centrally located atop the diode elements, an alignment accuracy of .+-.5 microns is necessary to assure fabrication of a useful element. Obviously, such high degrees of accuracy are difficult to attain and maintain over the surface of devices which may be 400 square centimeters. The situation is further complicated by the fact that because of the interrelationship of the diode elements, 100% yield is required. It should therefore be readily apparent that either the elimination of the alignment step or the relaxation of these alignment tolerances would result in improved device yields and decreased production costs.
One approach to the problem of alignment in arrays of solid state, micron size diode elements involves the use of a cross-over structure, in which a large body of semiconductor alloy material is sandwiched between a matrix of electrode forming lines disposed in two parallel, but vertically intersecting planes. While the semiconductor alloy material is disposed everywhere between the two planes, it effectively forms diodes only at those cross-over points at which the electrode lines intersect, owing to the relatively high lateral resistivety of the thin film semiconductor alloy material so employed. Such a cross-over device requires only two masking steps, for the formation of the two planar arrays of electrically conductive lines. Furthermore, high degrees of misalignment can be tolerated. There are however, several drawbacks to such a configuration. Since the body of semiconductor alloy material is disposed immediately beneath an upper plane of electrodes, some current spreading can occur, particularly if certain of the layers from which the body of semiconductor alloy material are relatively highly doped (and hence more conductive). Current spreading can establish a shunt path which deteriorates device performance, and when the spacing between adjacent electrode lines in a plane is micron-scale, can also initiate cross-talk. Furthermore, many semiconductor films are light sensitive, i.e., they are photoconductive, and in such instances no portion of the semiconductor alloy body of the cross-over diode structure can be exposed to illumination because the inherent photoconductive characteristics of the semiconductor would cause it to become more highly conductive, thereby further increasing shunt current paths and cross-talk.
Various other methods have been implemented toward the objective of eliminating masking steps in the production of arrays of micron-scale circuit elements on large area substrates. For instance, processes have been implemented by scientists working with the fabrication of thin film, solid state transistor elements in which one or more of the electrode members serves as a mask for superjacent photoresist layers. In this manner, the photoresist may be patterned without the use of an external mask, thereby providing for substantially unerring alignment and 100% yields in the processing step. Such techniques are referred to as self-masking or self-aligning processes. Such techniques for transistor fabrication are disclosed, for example, in a paper entitled "A Self Alignment Process For Amorphous Silicon Thin Film Transistors". IEEE Electron Device Letters. Vol. EDL-3 no. 7. July 1982. pp. 187-189 by Kodama. et al. and in a paper entitled "a-Si: H TFT: Potential Suitabilities for Gate and Source-Drain Self-Aligned Structure". Mat. Res. Soc. Symp. Proc. Vol. 33 (1984) pp. 281-285 by B. Diem. et al.
While the techniques disclosed in the foregoing publications are useful for the fabrication of amorphous thin film transistors, they do require that the radiation utilized to activate the photoresist be projected through the body of amorphous silicon semiconductor alloy material. This presents problems insofar as most photoresists are exposed with near ultraviolet radiation, typically radiation of approximately 360 nanometers. Such radiation is very strongly absorbed by amorphous silicon alloy materials and consequently, long exposure times and high energy fluxes must be utilized, which radiation wave-lengths and power levels can, in some cases, damage the semiconductor alloy material from which the transistors are fabricated.
Therefore, a process is needed for the fabrication of large area arrays of solid state, micron-scale circuit elements, which process does not necessitate precise mask alignment or registration steps and which process does not necessitate the projection of relatively high levels of radiation through the semiconductor alloy material from which the devices are fabricated. Such a technique could be utilized with great advantage in the fabrication of large area arrays of photosensors as well as for fabrication of large area thin film liquid crystal displays.
As mentioned hereinabove, large area displays are particularly prone to loss of operational efficiency due to the presence of defective discrete circuit elements therein, such as defective elements resultant from misalignment of masks. While in many solid state semiconductor arrays, yields of usable circuit elements of 90-95 percent are sufficient, the constraints upon liquid crystal displays are far more severe. A single defective pixel in a display device will result in a flaw immediately and glaringly visib1e to the user of thereof. Such flaws may be aesthetically displeasing and, in the instances where critical data is being transmitted, may be of significant importance. In a typical liquid crystal display device, a yield of 99.995% is unacceptable. Just as a chain is only as strong as its weakest link, a liquid crystal display is limited by the performance of its weakest picture element; consequently, nothing but 100% yield of reliable micron-scale solid state circuit elements is tolerable.
The instant invention provides a method for the fabrication of arrays of solid state circuit elements formed of semiconductor alloy material, which method eliminates a critical, precision masking step. For example, by utilizing the method of the instant invention, an array of diode circuit elements may be manufactured utilizing only two patterning masks. In contrast, prior art methods utilized three or more such masking steps and since the cumulative effect of errors resultant from masking rises exponentially, it should be evident that the elimination of even a single masking step significantly improves the yields of useable circuit elements.
According to the techniques disclosed herein, a large area semiconductor device formed from an array of discrete solid state, micron-scale circuit elements may be fabricated by a process in which portions of those elements being fabricated function to mask overlying photoresist layers for purposes of patterning an insulating oxide film disposed thereupon. Since the circuit elements are discrete, and since the portions of the oxide film being patterned overlie substantially all of the circuit elements, the radiation utilized to activate that photoresist need not penetrate through the body of semiconductor alloy material of the elements, but may merely pass through the interstitial portions of the substrate which have no semiconductor alloy material deposited thereupon. In this manner, attenuation of the activating radiation by the body of semiconductor alloy material and possible damage to that semiconductor alloy material by the radiation is eliminated.
These and other advantages of the instant invention will be apparent from the claims, the drawings and the detailed description thereof which follows.